100+ Gbps Ethernet Forward Error Correction (FEC) Analysis
Thu. January 31| 2:00 PM - 2:40 PM | Ballroom G
Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass
Track: 10. High-Speed Signal Processing, Equalization & Coding
Audience Level: All
Session Type: Technical Session
Description: In this study, high-speed serial link error propagation models and different Ethernet PMA/PCS schemes have been built and simulated to provide FEC performance analysis for 100/200/400GbE systems with 100+Gb/s per lane PAM4 interface. Different scenarios such as 1/(1+D) mod4 precoding, PMA bit multiplexing, symbol multiplexing and PCS RS codeword interleaving and their impacts on overall FEC performance will be discussed. Multi-part link where a single FEC shared between electrical and optical parts is studied as well. Advanced FEC schemes over current KP4 code will be explored at the end.
Takeaway: This study will provide comprehensive analysis for FEC performance for next generation 100Gb/s per lane 100/200/400GbE system.
R&D Director, OIF Board Member