Case Studies Isolating Types of Power Integrity Effects on Signal Integrity & Means of Mitigation

Wed. January 30| 9:00 AM - 9:45 AM | Ballroom F

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 02. Chip I/O & Functional Block Modeling & Validation Solutions

Audience Level: Intermediate

Session Type: Technical Session

Description: The interaction between power and signal integrity is often complicated and confusing. With the single-ended DDR5 bus reaching the same data rates as many popular differential SerDes channels, a better understanding of this interaction becomes more crucial. In this paper we discuss the three primary methods that power and signal integrity interact with each other, and present multiple cases that demonstrate situations where such interactions occur, with a focus on the impact on DDR5.

Takeaway: The signal and power integrity interaction in parallel interfaces are becoming more of problem due to the elevate speeds (4266-6400 MT/s) required by DDR5 interfaces. This paper presents a comprehensive understanding of the primary interaction/issues in designing such interfaces. It also presents how to identify the sources of these interactions and how to mitigate them and/or alleviate them when/if they do occur.


Speakers

Nitin Bhagwath

Nitin Bhagwath

Product Architect

Mentor, A Siemens Business

Role: Speaker

Rula Bakleh

Rula Bakleh

SI/PI Expert

Samtec Teraspeed Consulting

Role: Speaker