Electrical Integrity for LPDDR5 Memory Technology

Wed. January 30| 10:00 AM - 10:45 AM | Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation

Audience Level: Intermediate

Session Type: Technical Session

Description: LPDDR5 is an emerging memory technology for Low Power small form factor electronic design systems. LPDDR power delivery operating range is getting reduced in subsequent generations. Also, the signal integrity requirements are getting stringent as the speeds of the operation are increasing. It is becoming challenging to system design engineers to comply to the JEDEC specifications. In this paper we describe the specification trends and various techniques that can be used to meet electrical requirements including power integrity, signal integrity, thermal integrity, power and performance.

Takeaway: This paper describes LPDDR5 memory technologies constraints for Power Delivery, Power Integrity, Power and performance, Thermal, and explains system/platform design recommendations to meet those requirements.


Speakers

Vishram Pandit

Vishram Pandit

Platform Architect

Intel Technology India Pvt. Ltd

Role: Speaker

Aiswarya Pious

Aiswarya Pious

System Architect

Intel Corporation

Role: Speaker

Prabhat Ranjan

Prabhat Ranjan

Signal Integrity Engineer

Intel Technology India Pvt Ltd

Role: Speaker

Arvindh Rajasekaran

Arvindh Rajasekaran

Analog Engineer

Intel

Role: Speaker

Kirankumar Kamisetty

Kirankumar Kamisetty

Senior Analog Engineer

Intel, Oregon USA

Role: Author

Jun Liao

Jun Liao

Technical Lead for Memory Subsystem Electrical Design

Intel Hillsboro

Role: Author

Nagi Aboulenein

Nagi Aboulenein

Lead Client Memory System Architect

Role: Author

Christopher Cox

Christopher Cox

Memory Design Architect

Intel Folsom

Role: Author