Panel – PCI Express Ecosystem: Getting Ready for 32 GT/s

Wed. January 30| 3:45 PM - 5:00 PM | Ballroom C

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: 08. Optimizing High-Speed Serial Design

Audience Level: All

Session Type: Panel Discussion (Free)

Description: The PCI Express ecosystem will soon make a generational leap, doubling to 32GT/s. Our panel highlights the challenges in designing, implementing, and validating a new generation of PCI Express. We review the critical silicon to silicon questions: Is Gen5 PHY destined to use more DFE and more power? How to navigate controller and switch options? How do I know a cable or connector is 32G capable? What scope BW is required? Is the package more important at 32G? What channel optimization is needed? What potential add in card improvements?

Takeaway: As PCI Express speeds increase, so do the challenges. The attendees will gain important insights from leading experts in the design, implementation, and validation for PCI Express at 32GT/s.


Speakers

Steve Krooswyk

Steve Krooswyk

New Connector SI Design

Samtec

Role: Speaker

Pegah Alavi

Pegah Alavi

Senior Applications Engineer

Keysight

Role: Speaker

Rita Horner

Rita Horner

Sr. Technical Marketing Manager

Synopsys

Role: Speaker

Mo Liu

Mo Liu

PCIe SI Lead

Intel

Role: Speaker

Rick Eads

Rick Eads

Principal PCI Express Program Manager

Keysight

Role: Speaker

Dean Gonzales

Dean Gonzales

SI Lead

AMD

Role: Speaker

Alfred Key

Alfred Key

PCIe Product Architect for Board and Systems

NVIDIA

Role: Speaker