Tutorial – Design & Verification for High-Speed I/Os at 10 to 112Gbps With Jitter, Signal Integrity & Power Optimization
Tue. January 29| 1:30 PM - 4:30 PM | Ballroom D
Pass Type: All Access Pass, Alumni All Access Pass
Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors
Audience Level: All
Session Type: Tutorial
Takeaway: Basics knowledge on high-speed link architectures, jitter, noise, SNDR, nonlinearity, signal integrity, and related standards, design and verification methodologies, as well as the latest knowledge on the advanced topics such as 10-112 Gbps link design and verification with jitter, noise, SNDR, signal integrity, FEC/performance, and power optimization.