Tutorial – Design & Verification for High-Speed I/Os at 10 to 112Gbps With Jitter, Signal Integrity & Power Optimization

Tue. January 29| 1:30 PM - 4:30 PM | Ballroom D

Pass Type: All Access Pass, Alumni All Access Pass

Track: 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors

Audience Level: All

Session Type: Tutorial

Description: This TecForum reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process (28, 20, 14, 10 nm) technology advancements for high-speed links, with an emphasis on jitter, noise, signal integrity, and FEC for 10 -112 Gbps high-speed I/Os (e.g., GbE (10G, 40G, 100G, 200G, 400G), CEI/OIF (11G, 20-28G, 40-60G, 80-120G), Fibre Channel (16G, 32G, 64G, 128G), and PCI Express (8G, 16G, 32G). Example studies on design and validation methods will be presented.

Takeaway: Basics knowledge on high-speed link architectures, jitter, noise, SNDR, nonlinearity, signal integrity, and related standards, design and verification methodologies, as well as the latest knowledge on the advanced topics such as 10-112 Gbps link design and verification with jitter, noise, SNDR, signal integrity, FEC/performance, and power optimization.


Speakers

Mike Li

Mike Li

Fellow

Intel

Role: Speaker