PCI Express 5.0: Full Speed Ahead! Phy Layer Testing Challenges at 32GT/s

Wed. January 30| 9:20 AM - 10:05 AM | Great America 1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Sessions

Audience Level: Intermediate

Session Type: Sponsored Session

Description: Only two years in the making, PCI Express 5.0 is quickly following on the heels of the PCIe 4.0 specification and is expected to be finalized in H1 2019. At speeds of 32GT/s, and across channels that conspire to attenuate the 32GT/s signal by up to -38dB of loss at 16Ghz, PCIe 5.0 portends to become the most challenging edition of the PCI Express standard to date. In this session you will learn about some of the key differences between PCI Express 5.0 and PCie 4.0 including changes to the Gen5 receiver equalization requirements along with new options for link equalization. Especially challenging for Gen5 is the need to be able to tolerate a eye height of just over 10mV which is expected to push receiver technology to the brink. In this session you'll learn not only what's new with the PCIe 5.0 standard but also what to look for as you evaluate tools to help you evaluate your transmitter and receiver circuits.


Session Sponsor


Speakers

Rick Eads

Rick Eads

Principal Program Manager for Serial Computer Bus Technologies

Keysight Technologies

Role: Speaker

Thorsten Goetzelmann

Thorsten Goetzelmann

Application Engineer Receiver Test

Keysight Technologies

Role: Speaker