Design & Development of DDR5 IBIS-AMI Models

Wed. January 30| 11:05 AM - 11:45 AM | Mission City M1

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass, Boot Camp Pass, Expo Pass

Track: Sponsored Sessions

Session Type: Sponsored Session

Description: DDR5 is the next generation of high-speed DDRx memories expected to double the bandwidth of DDR4. To achieve these dramatic speed improvements, both controller and memory IO will need to adopt various equalization capabilities. These new features have required the model providers to adopt the capabilities of IBIS-AMI to properly model both the analog and equalization characteristics of the interface. This presentation will highlight key technology changes between DDR4 and DDR5, discuss the modeling environment requirements for time domain analysis, statistical analysis, and design regression, and finally describe the actual design and generation of IBIS-AMI DDR5 models.


Session Sponsor


Speakers

Douglas Burns

Douglas Burns

Vice President/Director of Support & Consulting Services

SiSoft (Signal Integrity Software, Inc.)

Role: Speaker

Justin Butterfield

Justin Butterfield

Senior Engineer: Silicon Signal Integrity

Micron Technology Inc.

Role: Speaker

Randy Wolff

Randy Wolff

Principal Engineer, Silicon Signal Integrity Lead

Micron Technology Inc.

Role: Speaker

Walter Katz

Walter Katz

Chief Scientist

Signal Integrity Software Inc. (SiSoft)

Role: Speaker