Machine Learning Applications for Simulation & Modeling of 56 & 112-Gb SerDes Systems

Thu. January 31| 9:00 AM - 9:45 AM | Ballroom B

Pass Type: 2-Day Pass, All Access Pass, Alumni All Access Pass

Track: 15. Machine Learning for Microelectronics, Signaling & System Design

Audience Level: All

Session Type: Technical Session

Description: This work describes a method for high-precision SerDes system modeling, and a predictive compliance simulation of high speed serial interfaces applicable for 25/56/112 Gb rates PAM4 and NRZ signaling. This method provides an accurate parametric macromodel using Machine Learning (ML) methods applied on measurement data, taking into account the controlled and uncontrolled variation in manufacturing tolerances as well as variation by design. The measurement based macromodel describes the system response with high precision for each case of interest, thus enabling an accurate compliance prediction. The method allows a high volume of simulation without requiring a high computational power.

Takeaway: Modeling 112 Gb SerDes systems, using Machine Learning (ML) methods applied on a measurement data. Learn how to take into account the controlled and uncontrolled variation in manufacturing tolerances as well as variation by design. Learn how to simulate 25/56/112 Gb PAM4 and NRZ systems accurately predicting compliance metrics.


Speakers

Adam J Norman

Adam J Norman

Engineer

Intel

Role: Speaker

Roee Bloch

Roee Bloch

Hi Speed Engineer

Intel

Role: Author

Alex Manukovsky

Alex Manukovsky

Technical lead, SI/PI team

Intel

Role: Speaker

Yaron Juniman

Yaron Juniman

Senior SI Engineer

Intel

Role: Author

Zurab Khasidashvili

Zurab Khasidashvili

Senior Software Engineer

Intel

Role: Author